Lead and manage a team of talented domain experts, software engineers, and performance optimization engineers to adapt HPC applications to run on AMD hardware Understand the challenges of resolving difficult software and system issues, support and advise engineers in the process of resolution. Drive the delivery of Exascale ready applications to AMD business units and cus

Coordinate test and quality requirements across SoC, IP and Product teams Lead DFT design and STA optimizations to meet design Power/Performance and Area targets Integrate scan control and test compression logic construction to achieve synthesis and physical design requirement Participate in DRC, test generation and test pattern validation to achieve high test fault cover

Conduct detailed investigations into a range of employee relations concerns such as harassment, discrimination, retaliation, and workplace violence, adhering to all applicable rules, regulations, policies, and procedures. Manage performance based casework, aligning closely with our Performance Management process. Provide clear, timely communication regarding investigation

Drive initial floorplan through pathfinding, identify critical cuts, identify routing channels, minimize whitespace with goal of minimum die size Support the floorplan through the design until tapeout Collaborate with CAD to continuously improve the floorplanning tools, flows, and methodology Dive deep into any area as needed and work across more than one program at a tim

Design, and implement high performance runtime features for AIE enabled devices that accelerates ML workloads. Work with technical leads and others to converge on the design of runtime software components. Collaborate with cross functional engineering teams to implement and debug software stack on AIE enabled device as required. PREFERRED EXPERIENCE Strong software develo

Develop and optimize key Deep Learning models on AMD GPUs Optimize deep learning frameworks like TensorFlow, PyTorch , etc. on AMD GPUs in upstream open source repositories Collaborate and interact with internal GPU library teams to analyze and optimize training and inference for deep learning Work with open source framework maintainers to understand their requirements an

Support the bi weekly US payroll processing for ~7000+ employees utilizing the ADP Vantage payroll system, ensuring accuracy and compliance. Process Termination Final payments and all other off cycle payment runs. Ensure accurate and timely processing and reporting of all payroll processes and all subsequent responsibilities. Perform validations of payroll inputs, down st

Accountable to track and debug for design issues and customer observation Ownership of internal and external issue triage in coordination with cross functional stakeholders in a matrix organization Coordinates end to end emulation demand roll up and is primary advocate to ensure program needs are achieved. Identifying technology and feature risk areas. Accountable for dev

Isolate generic system level failures into a more focused area of the platform or CPU Drive debug and resolution of Zen CPU validation issues across silicon, firmware/BIOS, and coordinating with memory partners as needed Devise validation strategy from pre silicon through customer adoption working across architecture, silicon design, firmware, validation, and debug teams

Memory Sub system Validation Engineer's responsibility includes all aspects of pre and post silicon validation from planning, execution and debug. Develop and execute test plans for HBM Functional and Electrical Validation (PVT Shmoo Characterization). The sought after candidate possess extensive knowledge of high bandwidth memory subsystem, including SoC memory architect

Implement and optimize GPU kernels using cutting edge compiler technology Conduct benchmarking on prevalent AI model workloads, including tasks in vision, speech recognition, language processing and generative models Collaborate with AMD's architecture specialists to enhance future products Stay abreast of software and hardware trends and innovations, particularly in algo

Create strong links and relationships between AMD and Partner consumer marketing and Alliance teams Build links within regional marketing to enable strong relationships in region Develop and manage WW co marketing funds and program terms; Communicate strategies and fund guidelines to regions and own WW plan roll ups Partner with Lenovo on executing global and regional co

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD

Serve as the AMD technical owner of various 3 rd party SERDES and other mixed signal IP. Provide pre and post silicon IP leadership and support for SerDes PHYs and other mixed signal IP, in particular IP like PCIe, Ethernet, UCIe, USB, MIPI, and Display PHYs, plus PLLs and miscellaneous IOs and circuits. Work directly with 3 rd party IP vendors to support design transfer,

Develop and execute voltage and frequency curve characterization plans for HPC/ML frameworks Analyzing characterization data for process variation Characterize Process and Temperature corners for voltage and frequency margin Exploit core architecture bottlenecks to test and mitigate worst case scenarios Support prototyping experiments for implementing features that impact